Graph Matching - Based Algorithms for FPGA Segmentation Design yYao
نویسندگان
چکیده
Yao-Wen Chang1, Jai-Ming Lin1, and D. F. Wong2 1Department of Computer and Information Science, National Chiao Tung University, Hsinchu 300, Taiwan 2Department of Computer Sciences, University of Texas at Austin, Austin, Texas 78712, USA Abstract Process technology advances will soon make the one-million gate FPGA a reality. A key issue that needs to be solved for the large-scale FPGAs to realize their full potential lies in the design of their segmentation architectures [10]. Onedimensional segmentation designs have been studied to some degree in much of the literature; most of the previously proposed methods are based on stochastic or analytical analysis. In this paper, we address a new direction for studying segmentation architectures. Our method is based on graph-theoretic formulation. We rst formulate a net matching problem and present a polynomial-time optimal algorithm to solve the problem. Based on the solution to the problem, we develop an effective and e cient matching-based algorithm for FPGA segmentation designs. Experimental results show that our method signi cantly outperforms previous work. For example, our method achieves averages of 18.2% and 8.9% improvements in routability, compared with the work in [14] and the most recent work in [7], respectively. More importantly, our approaches are very exible and can readily extend to higherorder segmentation designs (e.g., twoor three-dimensional segmentation design, etc), which are crucial to the design of large-scale FPGAs.
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